TSMC's Kaohsiung Mini-Loop is homework for CoWoS tools

What happened

On September 21, 2026, TrendForce summarized Taiwanese local press, including Commercial Times and Economic Daily News, on TSMC’s advanced-packaging buildout around Kaohsiung. Construction of Baipu Industrial Park began that day, with TSMC expected to anchor the cluster. The company plans a modular Mini-Loop line to validate new equipment and process integration before tools enter CoWoS production. Local reporting, via TrendForce, puts the validation-efficiency aim at 25% to 50%. That is a claim about how fast a tool can be qualified. It is not an announcement of more wafer starts.

TrendForce’s reason for a Mini-Loop is that AI packages are getting larger, and many back-end equipment suppliers are smaller than the front-end lithography giants. They struggle to validate gear alone. Jun He, TSMC’s vice president of advanced packaging technology and service, is cited estimating CoWoS capacity growth above 80% a year through 2027, with growth continuing through 2029. TrendForce also says CoWoS-L still competes with Intel’s EMIB-T, and expects TSMC’s maturity and yield edge to keep CoWoS the mainstream AI packaging path through 2028. That competitive frame is TrendForce’s analysis.

ASE shows up in the same synthesis as a rumor with an address. ASE reportedly plans two facilities at Baipu, after breaking ground on a new Renwu site in April. If that spending happens, TSMC’s validation line would sit closer to ASE’s packaging and test work. “Reportedly” stays on the ASE plan.

The glass path is a separate thread. Commercial Times and Economic Daily, via TrendForce, say TSMC is exploring CoPoS, a panel-level approach that shifts substrates from round wafers toward square panels, and is developing glass-core substrates. That work includes through-glass vias, redistribution layers, and GPU and HBM integration at TSMC’s 3DIC research center in Japan. A July Economic Daily note, again via TrendForce, said a CoPoS pilot is being built and that the technology and yields may need about another year before customer production. TSMC has reportedly visited AUO’s Central Taiwan Science Park site more than once, in talks that cover both a possible facility deal and CoPoS. AUO’s large-panel and glass experience overlaps with what panel-level packaging needs. All of that is reported interest, not a signed factory handover.

One process line from the Commercial Times writeup is enough. For glass substrates, the favored via path is an ultrafast laser plus a wet etch. Inspection matters because microcracks can spread between vias and wreck yield. That is process color, not a customer qualification.

Why it matters

CoWoS scarcity headlines are loud. Tool validation is the boring reason they last. A Mini-Loop that shortens equipment insert cycles is how TSMC tries to scale packaging without waiting for every assembly house and tool maker to build its own pilot. ASE at Baipu, if it happens, is the overflow story landing next door. CoPoS and glass cores are the next substrate cycle after organic interposers strain under AI package sizes.

Set next to Intel’s EMIB-T, this story does not crown a winner. It shows TSMC spending on the unglamorous middle of the chain, validation loops and panel pilots, while local press tracks real estate near AUO. Site deals stay reportedly until the companies say so.

What to watch is TSMC describing Mini-Loop timing in its own words, ASE confirming Baipu spending, any disclosed AUO transaction, and CoPoS language moving from “about a year” to a named customer. The queue those tools would feed is the DigiTimes allocation note.